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Electronics & Comm. Engineering · 975 questions

ECE Interview Questions: VLSI, Embedded & Core for freshers and experienced engineers

ECE hiring splits three ways: semiconductor and VLSI (Qualcomm, Texas Instruments, Intel, Samsung, Synopsys, Cadence), embedded and automotive (Bosch, Continental, Tata Elxsi, LTTS), and the government route (ISRO, DRDO, BEL, BSNL via GATE). Fresher interviews test digital and analog fundamentals, signals and a microcontroller; experienced VLSI interviews go deep on RTL, STA, physical design and UVM, embedded interviews on firmware, RTOS and protocols.

Start practising free Free readiness check
B.Tech enrolment 2024-25
1.60 lakh
GATE EC 2025 registrations
97,394
Core VLSI/embedded fresher CTC
Rs 6-14 LPA

Three sections, one ladder

Core covers the campus and GATE/PSU technical round. Design covers the tools, codes and standards experienced hires are tested on. Industry covers plant, site and production practice.

ECE Core

Analog, digital, signals, comms, EM, devices

Network theory, analog & digital electronics, signals & systems, communication systems, electromagnetics & antennas, control, microprocessors, semiconductor devices, DSP, instrumentation and basic electrical — the campus technical round and GATE/ISRO/BEL interview spine.

VLSI Design

RTL, STA, synthesis, PD, UVM, DFT, low power

RTL design in Verilog/SystemVerilog, CMOS & device physics, static timing analysis, synthesis, physical design, UVM verification, DFT, low-power (UPF), analog/mixed-signal, memory & standard cells, SoC architecture (AMBA) and FPGA — the Qualcomm/Intel/TI/Synopsys/Cadence interview layer.

Embedded Systems

Embedded C, MCUs, protocols, RTOS, Linux, PCB

Embedded C & firmware, ARM Cortex-M peripherals, UART/SPI/I2C/CAN protocols, FreeRTOS/Zephyr, embedded Linux & drivers, PCB design, power & signal integrity, JTAG debugging, AUTOSAR/ISO 26262, IoT & wireless, secure boot/OTA and MISRA/IEC 61508 — the Bosch/Continental/Tata Elxsi/LTTS interview layer.

Who hires electronics & comm. engineers

  • VLSI: Qualcomm, Texas Instruments, Intel, Samsung, NVIDIA, AMD, Micron, MediaTek, Synopsys, Cadence
  • Embedded/automotive: Bosch, Continental, Aptiv, KPIT, LTTS, Tata Elxsi, Harman
  • Telecom: Ericsson, Nokia, Jio, Airtel, Tejas Networks
  • IT services hire the largest share of ECE graduates

Government route

  • GATE EC -> ISRO, DRDO, BEL, ECIL, BSNL, PSU E&T posts
  • UPSC ESE (E&T 121 posts in 2026)
  • ISRO Scientist/Engineer SC (113 Electronics posts in 2025)
GATE EC pattern setESE ET pattern setAll government jobs →

How the interview runs

  1. 1Online test: aptitude + role MCQs (TI: 20 aptitude + 20 analog/digital/embedded; Qualcomm: three timed sections with negative marking)
  2. 2Technical rounds: project first, then RC transients, op-amps, MOSFET regions, FSMs, setup/hold, Verilog, 8051/ARM, embedded C
  3. 3Intel adds a group discussion; Bosch asks 8051 block diagram and pointers
  4. 4Eligibility: CGPA 6.9 at Qualcomm, 65-70% at Bosch

What experienced engineers get asked

  • RTL: pipelining, CDC, FIFO depth, low-power UPF; STA: OCV, multicycle and false paths, PrimeTime
  • Physical design: floorplan to signoff, IR drop, EM, DRC/LVS; verification: SystemVerilog UVM, coverage, SVA
  • Embedded: FreeRTOS, AUTOSAR, UDS, CAN/LIN/Ethernet, bootloaders, MISRA C, ISO 26262, Yocto
  • Tools: Synopsys, Cadence, Siemens EDA, Vivado, Keil, Lauterbach, CANoe

Your level, your role

Pick where you are and what you are targeting; placd builds the prep journey and the mock-interview rounds from it.

Levels

  • Fresher · Core / PSU
    ISRO / DRDO / BEL / BSNL — GATE-style core + technical interview
  • Fresher · Private / Campus
    Qualcomm / TI / Bosch / Tata Elxsi — core + coding + HR
  • Engineer (2–5 yrs)
    2–5 yrs — RTL/STA or firmware/RTOS depth decides
  • Senior (5–10 yrs)
    5–10 yrs — architecture, signoff and debug ownership
  • Lead / Manager
    Lead / Manager — tape-out or product ownership; fundamentals still screened

Roles

  • VLSI / Semiconductor
    RTL, STA, PD, verification, DFT
  • Embedded / Firmware
    Embedded C, RTOS, protocols, drivers
  • Telecom / RF
    Communication systems, RF, 5G, antennas
  • Hardware / PCB
    Schematics, PCB, power, SI/EMC
  • Core PSU / ISRO / GATE
    ISRO, DRDO, BEL, BSNL, ECIL

Interview questions by topic

Browse any topic free. Answers and explanations are one free account away; the free readiness check gives you a scored taste of the mock interview.

Frequently asked

What is asked in an ECE fresher interview?

Universal gates and K-maps, flip-flops and counters, setup and hold time, FSM design, diode and BJT/MOSFET operation, op-amp feedback, sampling theorem, convolution, AM/FM, 8051 or ARM architecture, and embedded C basics such as volatile.

How do Qualcomm, Texas Instruments and Intel hire freshers?

A timed online test with sections on aptitude and your chosen profile (analog, digital or embedded), one or two technical interviews driven by your project and fundamentals, sometimes a group discussion, then HR.

What do VLSI interviews for experienced engineers cover?

RTL coding quality and clock-domain crossing, static timing analysis and constraints, synthesis trade-offs, physical design flow and signoff checks, UVM testbench architecture and coverage closure, DFT and low-power techniques.

What do embedded and automotive interviews ask?

Embedded C traps (volatile, ISRs, memory maps), RTOS scheduling and priority inversion, UART/SPI/I2C/CAN details, AUTOSAR layers, UDS diagnostics, bootloaders and secure boot, and debugging with JTAG and a logic analyser.

Guide

ECE Interview Questions 2026: VLSI, Embedded and Core PSU Routes

How Qualcomm, Texas Instruments, Intel, Bosch and ISRO interview ECE graduates, 30 questions with answers on digital, analog, signals, embedded C and STA, and a 4-week plan.

Read the guide

Other departments

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