ECE Interview Questions 2026: VLSI, Embedded and Core PSU Routes

Electronics and Communication is the third-largest branch, with about 1.60 lakh students enrolled in 2024-25 and 97,394 GATE EC registrations in 2025, and it has the most fragmented hiring of any branch. The majority of ECE graduates are hired by IT services, where the interview is aptitude, CS fundamentals and basic coding; that lane is covered at placd.in/products/cs-fundamentals. The core lanes are smaller and better paid: semiconductor and VLSI at Qualcomm, Texas Instruments, Intel, Samsung, NVIDIA, AMD, MediaTek, Synopsys and Cadence (Rs 6-14 LPA for core fresher roles, Rs 15-30 LPA at the top firms), embedded and automotive at Bosch, Continental, Aptiv, KPIT, LTTS and Tata Elxsi, and telecom at Ericsson, Nokia, Jio and Tejas.

The government route runs through GATE EC into ISRO (113 electronics posts in 2025), DRDO, BEL, ECIL and BSNL, and through ESE with 121 electronics posts in 2026. Every core lane opens with the same fundamentals - digital, analog, signals, a microcontroller - and then diverges, so this guide covers the shared core and the two big specialisations.

How the interview actually runs

Texas Instruments runs an online test of 20 aptitude and 20 profile questions (you choose analog, digital or embedded), then one or two technical interviews whose first 20-30 minutes are your project, then HR. Its analog questions are RC transients, op-amp feedback, MOSFET regions and current mirrors; its digital questions are FSMs, setup and hold, Verilog and architecture. Qualcomm uses a timed three-section test with negative marking and a CGPA cut-off of 6.9, then two interviews for hardware roles. Intel adds a group discussion and mixes C, data structures and operating systems with digital design and architecture. Bosch asks for the 8051 block diagram, universal gates, pointers and embedded C, with eligibility around 65-70%.

The technical panel pattern is stable across companies: project first, then fundamentals, then the specialisation you claimed on your resume. Claim VLSI and you will be asked to write Verilog on a whiteboard; claim embedded and you will be asked what volatile does and how an interrupt is serviced. Government interviews come after the GATE score and go deeper into your specialisation and, at ISRO, into current programmes.

Digital electronics and RTL questions

Q (fresher): Why are NAND and NOR called universal gates? A: Any Boolean function can be built from NAND alone or NOR alone, and in CMOS they are the natural, compact gate structures.
Q (fresher): What are setup and hold time? A: The window around the active clock edge during which the data input of a flip-flop must be stable: setup before the edge, hold after it; violating either risks metastability.
Q (fresher): How do you design an FSM safely in Verilog? A: Separate the state register, next-state logic and output logic; use non-blocking assignments in the clocked block, cover every state with a default, and use a synchronous or asynchronous reset consistently.
Q (fresher): What is the difference between blocking and non-blocking assignments? A: Blocking (=) executes in order within a block and models combinational logic; non-blocking (<=) schedules updates at the end of the time step and models flip-flops, avoiding race conditions.
Q (fresher): What is metastability and how do you handle a clock domain crossing? A: A flip-flop whose input changes inside its setup/hold window can hover between levels; a two-flop synchroniser resolves single-bit crossings and an asynchronous FIFO with Gray-coded pointers handles multi-bit data.
Q (experienced): How do you size an asynchronous FIFO? A: From the maximum burst length and the worst-case read-write rate mismatch, so the writer never overruns the reader during the longest period the reader can be stalled.

Analog electronics and devices questions

Q (fresher): What are the three regions of a MOSFET? A: Cut-off below threshold, linear or triode where the drain current depends on both gate and drain voltage, and saturation where the channel pinches off and current depends mainly on gate voltage.
Q (fresher): Why does negative feedback improve an amplifier? A: It trades gain for bandwidth, linearity, lower distortion and predictable input and output impedance set by the feedback network rather than the transistor.
Q (fresher): What is a current mirror? A: A circuit that copies a reference current into one or more branches using matched transistors sharing a gate voltage; it is the basic biasing block of analog ICs.
Q (fresher): What happens to the RC circuit's output when a step is applied? A: The capacitor voltage rises exponentially with time constant RC, reaching 63% at one time constant and about 99% at five.
Q (experienced): What does a bandgap reference do and why is it stable? A: It adds a voltage with negative temperature coefficient (a diode drop) to one with positive coefficient (the thermal voltage times a ratio) so the sum, near 1.2 V, is flat with temperature.
Q (experienced): How does a low-dropout regulator differ from a switching regulator? A: An LDO is a linear pass element with an error amplifier, quiet and simple but dissipating the whole headroom; a switching regulator is efficient over a wide ratio but needs an inductor and produces ripple.

Signals, communication and DSP questions

Q (fresher): State the sampling theorem. A: A band-limited signal is fully recoverable if it is sampled at more than twice its highest frequency; below that, aliasing folds high frequencies onto low ones.
Q (fresher): What is convolution used for? A: Computing the output of a linear time-invariant system as the input convolved with the impulse response; in the frequency domain it becomes multiplication.
Q (fresher): What fraction of AM power is in the sidebands at 100% modulation? A: One third; the carrier carries two thirds, which is why single-sideband and suppressed-carrier schemes are more power-efficient.
Q (fresher): Why is OFDM used in 4G and 5G? A: It splits a wideband channel into many orthogonal narrowband subcarriers, so each sees flat fading and equalisation is a single complex multiply per subcarrier, with a cyclic prefix absorbing multipath.
Q (fresher): What does the Z-transform do for a discrete system? A: It turns difference equations into algebraic ones, so stability is read from pole locations inside the unit circle and filters are designed from pole-zero placement.

Microcontrollers, embedded C and protocols questions

Q (fresher): What does the volatile keyword do? A: It tells the compiler the variable can change outside program flow - a hardware register or an ISR-shared flag - so every access reads memory and no access is optimised away.
Q (fresher): What must an interrupt service routine avoid? A: Long execution, blocking calls, printf and heap allocation, and unprotected shared data; it should set a flag or push to a queue and return quickly.
Q (fresher): What is the difference between I2C and SPI? A: I2C is a two-wire, addressed, multi-drop bus with open-drain lines and pull-ups at up to a few megahertz; SPI is a four-wire, chip-select-per-device, full-duplex bus at tens of megahertz with no addressing overhead.
Q (fresher): How does CAN arbitrate? A: Bit-wise on the identifier: a dominant zero overrides a recessive one, so the lowest identifier wins without destroying any frame, and CAN FD raises the data phase to up to 8 Mbit/s.
Q (fresher): What is priority inversion and how does an RTOS fix it? A: A high-priority task waiting on a mutex held by a low-priority task that is itself preempted by a medium one; priority inheritance temporarily raises the holder to the waiter's priority.
Q (experienced): What does secure boot protect against? A: Execution of unsigned or modified firmware; each stage verifies the signature of the next against a key rooted in hardware, forming a chain of trust from the boot ROM.

STA, physical design and verification questions for experienced engineers

Q (experienced): What is slack? A: Required time minus arrival time on a timing path; positive means the path meets timing, negative means a violation to be fixed by restructuring, sizing or retiming.
Q (experienced): What is on-chip variation and how is it handled? A: Process, voltage and temperature vary across a die, so setup is checked with the data path slow and the clock path fast, and hold with the reverse, using OCV, AOCV or POCV derates.
Q (experienced): What is a multicycle path? A: A path deliberately allowed more than one clock cycle; it must be constrained in the SDC so STA does not report a false setup violation.
Q (experienced): Why is clock tree synthesis done after placement? A: Because skew and insertion delay depend on where the flops landed; CTS balances the tree to the placed flops, then routing and signoff follow.
Q (experienced): What is the difference between code coverage and functional coverage in UVM? A: Code coverage measures which RTL lines, branches and toggles were exercised; functional coverage measures whether the scenarios in the verification plan actually occurred, via covergroups and assertions.
Q (experienced): What does a scan chain give you? A: A way to shift test patterns into every flip-flop and shift results out, turning sequential logic into combinational logic for ATPG and reaching stuck-at and transition faults.

What experienced engineers get asked

VLSI engineers (2-10 years) are interviewed on RTL quality - pipelining, CDC, FIFO sizing, low-power intent in UPF - on static timing analysis and constraints, synthesis trade-offs in Design Compiler or Genus, the physical design flow from floorplan to signoff with IR drop and electromigration checks, UVM testbench architecture and coverage closure, and DFT with scan, ATPG and BIST. Tools named in interviews are Synopsys, Cadence, Siemens EDA, Vivado and Quartus.

Embedded and automotive engineers are interviewed on FreeRTOS or Zephyr internals, AUTOSAR classic and adaptive layers, UDS diagnostics under ISO 14229, CAN, LIN and automotive Ethernet, bootloaders and over-the-air updates, MISRA C, ISO 26262 ASIL decomposition, embedded Linux with Yocto and device trees, and debugging with JTAG/SWD, Lauterbach trace and a logic analyser.

The government route

ISRO, DRDO, BEL and BSNL interviews follow the GATE score or their own written test. ISRO panels ask about your specialisation - RF, digital, embedded or communication - and about the systems the centre builds; BEL and DRDO panels stay close to the undergraduate core with an emphasis on radar, communication and defence electronics. ESE interviews add general awareness and a personality assessment. In all of them, fundamentals are derived on the board, not recalled.

A 4-week plan

Week 1: Digital electronics, analog electronics and semiconductor devices from the ECE Core section, 40 questions a day; write three small Verilog modules from scratch.
Week 2: Signals and systems, communication, DSP and microprocessors; take the free 2-minute readiness check on your stream.
Week 3: VLSI Design section (RTL, STA, synthesis, physical design, UVM) if you target semiconductor roles, or Embedded Systems (embedded C, peripherals, protocols, RTOS) if you target embedded and automotive roles.
Week 4: Recruiter pages for Qualcomm, Texas Instruments and Bosch, timed aptitude, and two full mock interviews at your target level.

All of the questions above are drawn from placd's ECE banks, about 975 questions across the core, VLSI and embedded sections with explanations. Start at the department hub, placd.in/engineering/ece, browse topics such as placd.in/questions/ece-core/digital-electronics, placd.in/questions/ece-vlsi/static-timing-analysis and placd.in/questions/ece-embedded/embedded-c-and-firmware, and sit the scored AI mock interview on Pro at placd.in/products/mock-interview (take the free readiness check first), with the interviewer asking from the ECE bank when you pick a VLSI or embedded role.