27 real Analog & Mixed-Signal Design questions from the VLSI Design bank, as asked in Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd — free to start.
1. What is Two-stage op-amp?
Junior
A.differential input stage followed by a common-source gain stage, Miller compensated with a capacitor across the second stage to place the dominant pole
B.linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
C.random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
D.cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock
2. Which term means: "differential input stage followed by a common-source gain stage, Miller compensated with a capacitor across the second stage to place the dominant pole"?
A.Two-stage op-amp — differential input stage followed by a common-source gain stage, Miller compensated with a capacitor across the second stage to place the dominant pole
B.Two-stage op-amp — circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
C.Two-stage op-amp — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
D.Two-stage op-amp — linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
A.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
B.substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones
C.oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
D.circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
5. Which term means: "circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature"?
A.Bandgap reference — linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
B.Bandgap reference — feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
C.Bandgap reference — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
D.Bandgap reference — circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
A.oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
B.differential input stage followed by a common-source gain stage, Miller compensated with a capacitor across the second stage to place the dominant pole
C.random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
D.linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
8. Which term means: "linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat"?
A.Low-dropout regulator — random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
B.Low-dropout regulator — cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock
C.Low-dropout regulator — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
D.Low-dropout regulator — linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
A.oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
B.random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
C.cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock
D.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
11. Which term means: "feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling"?
A.Phase-locked loop — oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
B.Phase-locked loop — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
C.Phase-locked loop — linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
D.Phase-locked loop — feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
A.Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
B.circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
C.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
D.cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock
14. Which term means: "cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock"?
A.Pipelined ADC — cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock
B.Pipelined ADC — oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
C.Pipelined ADC — circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
D.Pipelined ADC — random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
A.linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
B.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
C.oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
D.circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
17. Which term means: "oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors"?
A.Sigma-delta ADC — substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones
B.Sigma-delta ADC — differential input stage followed by a common-source gain stage, Miller compensated with a capacitor across the second stage to place the dominant pole
C.Sigma-delta ADC — oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
D.Sigma-delta ADC — feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
A.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
B.circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
C.oversampling converter pushing quantisation noise to high frequencies with a modulator loop and filtering it digitally, giving 16–24 bits for audio and sensors
D.Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
20. Which term means: "Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification"?
A.Virtuoso — feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
B.Virtuoso — random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
C.Virtuoso — substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones
D.Virtuoso — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
A.linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
B.random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
C.Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
D.cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock
23. Which term means: "random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation"?
A.Device matching — cascade of low-resolution stages each resolving bits and passing an amplified residue, achieving 10–14 bits at hundreds of MS/s with one sample per clock
B.Device matching — random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
C.Device matching — linear regulator with a pass transistor and error amplifier that holds output within a few hundred millivolts of input, quiet but dissipating the drop as heat
D.Device matching — substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones
A.substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones
B.circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
C.feedback loop of phase detector, charge pump, loop filter, VCO and divider that locks an output clock to a reference multiple, with bandwidth trading jitter against settling
D.random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
26. Which term means: "substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones"?
A.Guard rings and dummy devices — Cadence schematic and layout environment for custom IC design, with Spectre simulation, ADE assistants for corners and Monte Carlo, and integrated physical verification
B.Guard rings and dummy devices — circuit summing a VBE with negative temperature coefficient and a scaled ΔVBE with positive coefficient to give about 1.2 V nearly independent of temperature
C.Guard rings and dummy devices — random mismatch in threshold and current factor scales as Pelgrom's A/√(WL), so precision pairs use large area, common-centroid layout and identical orientation
D.Guard rings and dummy devices — substrate-tied rings around sensitive blocks isolate noise, and dummy fingers at array edges equalise etch and stress so edge transistors match interior ones
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