27 real Verification (UVM) questions from the VLSI Design bank, as asked in Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd — free to start.
1. What is UVM testbench layering?
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A.user-defined covergroups, coverpoints and crosses tied to the verification plan, measuring whether specified scenarios occurred rather than which code ran
B.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
C.IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database
D.ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
2. Which term means: "IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database"?
A.UVM testbench layering — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
B.UVM testbench layering — pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
C.UVM testbench layering — sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
D.UVM testbench layering — IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database
A.tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure
B.component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
C.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
D.generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
5. Which term means: "generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss"?
A.Constrained random verification — IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database
B.Constrained random verification — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
C.Constrained random verification — immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
D.Constrained random verification — user-defined covergroups, coverpoints and crosses tied to the verification plan, measuring whether specified scenarios occurred rather than which code ran
A.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
B.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
C.tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure
D.component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
8. Which term means: "tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure"?
A.Code coverage — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
B.Code coverage — tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure
C.Code coverage — pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
D.Code coverage — component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
A.generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
B.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
C.user-defined covergroups, coverpoints and crosses tied to the verification plan, measuring whether specified scenarios occurred rather than which code ran
D.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
11. Which term means: "user-defined covergroups, coverpoints and crosses tied to the verification plan, measuring whether specified scenarios occurred rather than which code ran"?
A.Functional coverage — pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
B.Functional coverage — immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
C.Functional coverage — user-defined covergroups, coverpoints and crosses tied to the verification plan, measuring whether specified scenarios occurred rather than which code ran
D.Functional coverage — sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
A.generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
B.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
C.component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
D.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
14. Which term means: "component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness"?
A.Scoreboard — sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
B.Scoreboard — ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
C.Scoreboard — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
D.Scoreboard — component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
A.tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure
B.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
C.pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
D.ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
17. Which term means: "sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake"?
A.UVM sequence and sequencer — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
B.UVM sequence and sequencer — user-defined covergroups, coverpoints and crosses tied to the verification plan, measuring whether specified scenarios occurred rather than which code ran
C.UVM sequence and sequencer — sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
D.UVM sequence and sequencer — ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
A.IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database
B.generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
C.pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
D.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
20. Which term means: "immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal"?
A.SystemVerilog assertions — ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
B.SystemVerilog assertions — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
C.SystemVerilog assertions — component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
D.SystemVerilog assertions — immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
A.immediate and concurrent properties built from sequences and implication operators |-> and |=> that check temporal protocol rules in simulation and formal
B.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
C.pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
D.IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database
23. Which term means: "pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers"?
A.Verification IP — ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
B.Verification IP — tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure
C.Verification IP — component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
D.Verification IP — pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
A.sequences generate transaction items and arbitrate through a sequencer that hands them to the driver via the get_next_item and item_done handshake
B.pre-verified licensed agents for standard protocols such as AXI, PCIe or DDR, including drivers, monitors, coverage models and protocol checkers
C.ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
D.tool-collected line, toggle, branch, condition and FSM metrics showing which RTL was exercised, necessary but not sufficient for closure
26. Which term means: "ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends"?
A.UVM phasing — component comparing transactions predicted by a reference model with those observed at the DUT output, flagging mismatches and tracking end-of-test completeness
B.UVM phasing — IEEE 1800.2 class library structuring a testbench as test, environment and agents with sequencer, driver and monitor, connected by TLM ports and a config database
C.UVM phasing — generating stimulus from randomised transactions bounded by constraints so the simulator explores legal corner cases a directed test would miss
D.UVM phasing — ordered build, connect, end_of_elaboration, run and report phases, with build executed top-down and connect bottom-up, and objections deciding when run ends
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