27 real Power & Signal Integrity questions from the Embedded Systems bank, as asked in Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd — free to start.
1. What is Decoupling capacitors?
Junior
A.shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
B.small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
C.series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time
D.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
2. Which term means: "small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail"?
A.Decoupling capacitors — shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
B.Decoupling capacitors — small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
C.Decoupling capacitors — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
D.Decoupling capacitors — linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
A.linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
B.small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
C.transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
D.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
5. Which term means: "linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count"?
A.LDO versus SMPS — trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
B.LDO versus SMPS — shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
C.LDO versus SMPS — linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
D.LDO versus SMPS — series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time
A.small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
B.shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
C.transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
D.residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
8. Which term means: "residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator"?
A.Output ripple — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
B.Output ripple — series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time
C.Output ripple — coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
D.Output ripple — small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
A.shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
B.linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
C.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
D.target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit
11. Which term means: "trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations"?
A.Controlled impedance — trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
B.Controlled impedance — transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
C.Controlled impedance — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
D.Controlled impedance — target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit
A.coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
B.linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
C.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
D.shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
14. Which term means: "coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference"?
A.Crosstalk — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
B.Crosstalk — transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
C.Crosstalk — linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
D.Crosstalk — coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
A.linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
B.small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
C.series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time
D.coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
17. Which term means: "series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time"?
A.Termination — trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
B.Termination — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
C.Termination — series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time
D.Termination — transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
A.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
B.shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
C.coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
D.transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
20. Which term means: "shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs"?
A.Ground bounce — residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
B.Ground bounce — shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
C.Ground bounce — coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
D.Ground bounce — linear regulator is simple and quiet but wastes (Vin − Vout)·I as heat; a switching regulator reaches 85–95% efficiency at the cost of ripple, EMI and component count
A.series resistor at the driver or parallel or Thevenin resistor at the receiver absorbing reflections once trace delay exceeds about one-sixth of the signal rise time
B.transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
C.coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
D.target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit
23. Which term means: "transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports"?
A.ESD and TVS protection — transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
B.ESD and TVS protection — target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit
C.ESD and TVS protection — small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
D.ESD and TVS protection — shift in a chip's internal ground when many outputs switch together through package inductance (L·di/dt), causing false logic levels and glitches on quiet outputs
A.target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit
B.residual AC on a regulator output at the switching frequency, set by inductor ripple current and output capacitor ESR and ESL, reduced by LC filtering or a post-regulator
C.transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
D.trace width, dielectric thickness and εr chosen so a single-ended line is 50 Ω or a differential pair 90 or 100 Ω, matching drivers and terminations
26. Which term means: "target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit"?
A.Power delivery network impedance — transient voltage suppressor diodes at connectors clamping strikes within nanoseconds, rated to IEC 61000-4-2 ±8 kV contact for consumer ports
B.Power delivery network impedance — small ceramics placed as close as possible to each supply pin to supply transient current and hold local voltage steady, backed by a bulk capacitor per rail
C.Power delivery network impedance — coupling of a switching aggressor into a neighbouring victim through mutual capacitance and inductance, reduced by 3W spacing, shorter parallel runs and a solid ground reference
D.Power delivery network impedance — target Z = ΔV/ΔI held across frequency by combining bulk, ceramic and on-die capacitance so anti-resonance peaks between them stay below the limit
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