VLSI Design

RTL, STA, synthesis, PD, UVM, DFT, low power

RTL design in Verilog/SystemVerilog, CMOS & device physics, static timing analysis, synthesis, physical design, UVM verification, DFT, low-power (UPF), analog/mixed-signal, memory & standard cells, SoC architecture (AMBA) and FPGA — the Qualcomm/Intel/TI/Synopsys/Cadence interview layer.

• RTL · STA · PD
• UVM · DFT · UPF
• Semiconductor roles 0–10 yrs
• Editorial solutions
• Progress tracking