27 real Memory & Standard Cells questions from the VLSI Design bank, as asked in Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd — free to start.
1. What is 6T SRAM cell?
Junior
A.single-error-correct double-error-detect Hamming or BCH code adding check bits per word, protecting against soft errors from alpha particles and neutrons
B.characterisation data giving cell delay, output transition, setup/hold and power as lookup tables against input slew and output load per corner
C.two cross-coupled inverters and two access transistors holding data statically while powered, with read stability set by cell ratio and write ability by pull-up ratio
D.SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
2. Which term means: "two cross-coupled inverters and two access transistors holding data statically while powered, with read stability set by cell ratio and write ability by pull-up ratio"?
A.6T SRAM cell — process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T
B.6T SRAM cell — single-error-correct double-error-detect Hamming or BCH code adding check bits per word, protecting against soft errors from alpha particles and neutrons
C.6T SRAM cell — characterisation data giving cell delay, output transition, setup/hold and power as lookup tables against input slew and output load per corner
D.6T SRAM cell — two cross-coupled inverters and two access transistors holding data statically while powered, with read stability set by cell ratio and write ability by pull-up ratio
A.one transistor and one capacitor storing charge that leaks, so rows are refreshed about every 64 ms and reads are destructive and rewritten
B.SRAM stability measured as the side of the largest square fitting inside the butterfly curve; it shrinks with voltage scaling and limits minimum operating VDD
C.process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T
D.SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
5. Which term means: "one transistor and one capacitor storing charge that leaks, so rows are refreshed about every 64 ms and reads are destructive and rewritten"?
A.DRAM cell — differential circuit detecting the small bitline split of around 100 mV and amplifying it to full logic levels quickly during a memory read
B.DRAM cell — process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T
C.DRAM cell — one transistor and one capacitor storing charge that leaks, so rows are refreshed about every 64 ms and reads are destructive and rewritten
D.DRAM cell — collection of pre-characterised logic and sequential cells of fixed height and pitch, delivered as .lib timing, LEF abstracts, GDS layout and SPICE models
A.process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T
B.two cross-coupled inverters and two access transistors holding data statically while powered, with read stability set by cell ratio and write ability by pull-up ratio
C.differential circuit detecting the small bitline split of around 100 mV and amplifying it to full logic levels quickly during a memory read
D.SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
8. Which term means: "differential circuit detecting the small bitline split of around 100 mV and amplifying it to full logic levels quickly during a memory read"?
A.Sense amplifier — SRAM stability measured as the side of the largest square fitting inside the butterfly curve; it shrinks with voltage scaling and limits minimum operating VDD
B.Sense amplifier — single-error-correct double-error-detect Hamming or BCH code adding check bits per word, protecting against soft errors from alpha particles and neutrons
C.Sense amplifier — differential circuit detecting the small bitline split of around 100 mV and amplifying it to full logic levels quickly during a memory read
D.Sense amplifier — SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
A.collection of pre-characterised logic and sequential cells of fixed height and pitch, delivered as .lib timing, LEF abstracts, GDS layout and SPICE models
B.SRAM stability measured as the side of the largest square fitting inside the butterfly curve; it shrinks with voltage scaling and limits minimum operating VDD
C.one transistor and one capacitor storing charge that leaks, so rows are refreshed about every 64 ms and reads are destructive and rewritten
D.single-error-correct double-error-detect Hamming or BCH code adding check bits per word, protecting against soft errors from alpha particles and neutrons
11. Which term means: "collection of pre-characterised logic and sequential cells of fixed height and pitch, delivered as .lib timing, LEF abstracts, GDS layout and SPICE models"?
A.Standard cell library — collection of pre-characterised logic and sequential cells of fixed height and pitch, delivered as .lib timing, LEF abstracts, GDS layout and SPICE models
B.Standard cell library — SRAM stability measured as the side of the largest square fitting inside the butterfly curve; it shrinks with voltage scaling and limits minimum operating VDD
C.Standard cell library — process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T
D.Standard cell library — SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
A.single-error-correct double-error-detect Hamming or BCH code adding check bits per word, protecting against soft errors from alpha particles and neutrons
B.one transistor and one capacitor storing charge that leaks, so rows are refreshed about every 64 ms and reads are destructive and rewritten
C.SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
D.characterisation data giving cell delay, output transition, setup/hold and power as lookup tables against input slew and output load per corner
14. Which term means: "characterisation data giving cell delay, output transition, setup/hold and power as lookup tables against input slew and output load per corner"?
A.Liberty (.lib) file — SRAM stability measured as the side of the largest square fitting inside the butterfly curve; it shrinks with voltage scaling and limits minimum operating VDD
B.Liberty (.lib) file — differential circuit detecting the small bitline split of around 100 mV and amplifying it to full logic levels quickly during a memory read
C.Liberty (.lib) file — single-error-correct double-error-detect Hamming or BCH code adding check bits per word, protecting against soft errors from alpha particles and neutrons
D.Liberty (.lib) file — characterisation data giving cell delay, output transition, setup/hold and power as lookup tables against input slew and output load per corner
A.differential circuit detecting the small bitline split of around 100 mV and amplifying it to full logic levels quickly during a memory read
B.process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T
C.SRAM stability measured as the side of the largest square fitting inside the butterfly curve; it shrinks with voltage scaling and limits minimum operating VDD
D.two cross-coupled inverters and two access transistors holding data statically while powered, with read stability set by cell ratio and write ability by pull-up ratio
17. Which term means: "process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T"?
A.PVT corners — process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T
B.PVT corners — SRAM stability measured as the side of the largest square fitting inside the butterfly curve; it shrinks with voltage scaling and limits minimum operating VDD
C.PVT corners — collection of pre-characterised logic and sequential cells of fixed height and pitch, delivered as .lib timing, LEF abstracts, GDS layout and SPICE models
D.PVT corners — SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
A.characterisation data giving cell delay, output transition, setup/hold and power as lookup tables against input slew and output load per corner
B.two cross-coupled inverters and two access transistors holding data statically while powered, with read stability set by cell ratio and write ability by pull-up ratio
C.SRAM stability measured as the side of the largest square fitting inside the butterfly curve; it shrinks with voltage scaling and limits minimum operating VDD
D.SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
20. Which term means: "SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate"?
A.Library characterisation — process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T
B.Library characterisation — one transistor and one capacitor storing charge that leaks, so rows are refreshed about every 64 ms and reads are destructive and rewritten
C.Library characterisation — SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
D.Library characterisation — differential circuit detecting the small bitline split of around 100 mV and amplifying it to full logic levels quickly during a memory read
A.process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T
B.SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
C.single-error-correct double-error-detect Hamming or BCH code adding check bits per word, protecting against soft errors from alpha particles and neutrons
D.SRAM stability measured as the side of the largest square fitting inside the butterfly curve; it shrinks with voltage scaling and limits minimum operating VDD
23. Which term means: "SRAM stability measured as the side of the largest square fitting inside the butterfly curve; it shrinks with voltage scaling and limits minimum operating VDD"?
A.Static noise margin — differential circuit detecting the small bitline split of around 100 mV and amplifying it to full logic levels quickly during a memory read
B.Static noise margin — process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T
C.Static noise margin — characterisation data giving cell delay, output transition, setup/hold and power as lookup tables against input slew and output load per corner
D.Static noise margin — SRAM stability measured as the side of the largest square fitting inside the butterfly curve; it shrinks with voltage scaling and limits minimum operating VDD
A.one transistor and one capacitor storing charge that leaks, so rows are refreshed about every 64 ms and reads are destructive and rewritten
B.characterisation data giving cell delay, output transition, setup/hold and power as lookup tables against input slew and output load per corner
C.single-error-correct double-error-detect Hamming or BCH code adding check bits per word, protecting against soft errors from alpha particles and neutrons
D.SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
26. Which term means: "single-error-correct double-error-detect Hamming or BCH code adding check bits per word, protecting against soft errors from alpha particles and neutrons"?
A.ECC in memories — SPICE simulation of each cell across slews, loads and corners to produce .lib tables, using tools such as SiliconSmart or Liberate
B.ECC in memories — process, voltage and temperature combinations at which timing is verified, with worst setup at slow/low-V/high-T and worst hold at fast/high-V/low-T
C.ECC in memories — single-error-correct double-error-detect Hamming or BCH code adding check bits per word, protecting against soft errors from alpha particles and neutrons
D.ECC in memories — characterisation data giving cell delay, output transition, setup/hold and power as lookup tables against input slew and output load per corner
Answers, AI explanations, and a free readiness check
Sign up free to check your answers with explanations, ask the AI tutor anything on any question, and take the free 2-minute readiness check for a scored result. The full AI mock interview, scored like a real panel, unlocks with Pro.