27 real Digital Electronics questions from the ECE Core bank, as asked in Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd — free to start.
1. What is Universal gates?
Junior
A.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
B.NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
C.in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
D.combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
A.Universal gates — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
B.Universal gates — NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
C.Universal gates — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
D.Universal gates — converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input
A.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
B.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
C.flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
D.complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
5. Which term means: "complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms"?
A.De Morgan's theorems — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
B.De Morgan's theorems — flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
C.De Morgan's theorems — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
D.De Morgan's theorems — combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
A.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
B.complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
C.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
D.combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
8. Which term means: "combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables"?
A.Multiplexer — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
B.Multiplexer — combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
C.Multiplexer — asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
D.Multiplexer — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
A.in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
B.combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
C.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
D.static cell of six transistors holds data without refresh and is fast; dynamic cell of one transistor and one capacitor is denser and cheaper but needs periodic refresh
11. Which term means: "static cell of six transistors holds data without refresh and is fast; dynamic cell of one transistor and one capacitor is denser and cheaper but needs periodic refresh"?
A.SRAM versus DRAM — static cell of six transistors holds data without refresh and is fast; dynamic cell of one transistor and one capacitor is denser and cheaper but needs periodic refresh
B.SRAM versus DRAM — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
C.SRAM versus DRAM — NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
D.SRAM versus DRAM — converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input
A.in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
B.complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
C.flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
D.NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
14. Which term means: "in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction"?
A.Race-around condition — NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
B.Race-around condition — combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
C.Race-around condition — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
D.Race-around condition — in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
A.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
B.converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input
C.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
D.complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
17. Which term means: "asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count"?
A.Ripple versus synchronous counter — combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
B.Ripple versus synchronous counter — converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input
C.Ripple versus synchronous counter — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
D.Ripple versus synchronous counter — asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
A.NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
B.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
C.converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input
D.in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
20. Which term means: "Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change"?
A.Mealy versus Moore machine — in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
B.Mealy versus Moore machine — Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
C.Mealy versus Moore machine — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
D.Mealy versus Moore machine — combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
A.converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input
B.in a level-triggered J-K flip-flop with J = K = 1 the output toggles repeatedly while the clock is high, cured by edge triggering or master-slave construction
C.NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
D.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
23. Which term means: "converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input"?
A.Successive approximation ADC — static cell of six transistors holds data without refresh and is fast; dynamic cell of one transistor and one capacitor is denser and cheaper but needs periodic refresh
B.Successive approximation ADC — flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
C.Successive approximation ADC — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
D.Successive approximation ADC — converter performing a binary search with a DAC and comparator, taking n clock cycles for n bits and needing a sample-and-hold at the input
A.Moore output depends on present state only; Mealy output depends on state and input, generally needing fewer states but able to glitch when inputs change
B.combinational circuit routing one of 2^n data inputs to a single output under n select lines, able to implement any Boolean function of n + 1 variables
C.flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
D.asynchronous stages clock each other so delays accumulate and limit speed; synchronous stages share one clock and the maximum frequency is independent of stage count
26. Which term means: "flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs"?
A.Metastability — complement of a product equals the sum of the complements and complement of a sum equals the product of the complements, converting between AND-OR and NAND-NOR forms
B.Metastability — flip-flop state where the output hovers between logic levels for an unbounded time after a setup or hold violation, mitigated by two-stage synchronisers on asynchronous inputs
C.Metastability — static cell of six transistors holds data without refresh and is fast; dynamic cell of one transistor and one capacitor is denser and cheaper but needs periodic refresh
D.Metastability — NAND and NOR, either of which alone can realise any Boolean function, so a design can be built from a single gate type
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