27 real Microcontrollers & Peripherals questions from the Embedded Systems bank, as asked in Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd — free to start.
1. What is ARM Cortex-M NVIC?
Junior
A.Wi-Fi and Bluetooth SoCs with dual Xtensa LX6/LX7 or single RISC-V cores, running ESP-IDF on FreeRTOS with one core commonly reserved for the wireless stack
B.nested vectored interrupt controller with programmable priorities, pre-emption, tail-chaining and automatic register stacking so handlers are ordinary C functions
C.timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement
D.sleep stops only the core, stop halts most clocks with RAM retained and microsecond wake-up, standby powers down to a few microamps with only RTC and wake-up pins alive
2. Which term means: "nested vectored interrupt controller with programmable priorities, pre-emption, tail-chaining and automatic register stacking so handlers are ordinary C functions"?
A.ARM Cortex-M NVIC — Wi-Fi and Bluetooth SoCs with dual Xtensa LX6/LX7 or single RISC-V cores, running ESP-IDF on FreeRTOS with one core commonly reserved for the wireless stack
B.ARM Cortex-M NVIC — sleep stops only the core, stop halts most clocks with RAM retained and microsecond wake-up, standby powers down to a few microamps with only RTC and wake-up pins alive
C.ARM Cortex-M NVIC — internal and external oscillators feeding a PLL and prescalers for the system, AHB and APB clocks, with flash wait states set for speed and peripheral clocks enabled before register access
D.ARM Cortex-M NVIC — nested vectored interrupt controller with programmable priorities, pre-emption, tail-chaining and automatic register stacking so handlers are ordinary C functions
A.independent counter that resets the MCU if not refreshed within its timeout; a windowed variant also rejects refreshes that arrive too early, catching runaway loops
B.Wi-Fi and Bluetooth SoCs with dual Xtensa LX6/LX7 or single RISC-V cores, running ESP-IDF on FreeRTOS with one core commonly reserved for the wireless stack
C.each pin set as input, output, alternate function or analog, with push-pull or open-drain driver, pull-up or pull-down selection and output speed setting
D.timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement
5. Which term means: "each pin set as input, output, alternate function or analog, with push-pull or open-drain driver, pull-up or pull-down selection and output speed setting"?
A.GPIO configuration — Wi-Fi and Bluetooth SoCs with dual Xtensa LX6/LX7 or single RISC-V cores, running ESP-IDF on FreeRTOS with one core commonly reserved for the wireless stack
B.GPIO configuration — independent counter that resets the MCU if not refreshed within its timeout; a windowed variant also rejects refreshes that arrive too early, catching runaway loops
C.GPIO configuration — nested vectored interrupt controller with programmable priorities, pre-emption, tail-chaining and automatic register stacking so handlers are ordinary C functions
D.GPIO configuration — each pin set as input, output, alternate function or analog, with push-pull or open-drain driver, pull-up or pull-down selection and output speed setting
A.each pin set as input, output, alternate function or analog, with push-pull or open-drain driver, pull-up or pull-down selection and output speed setting
B.internal and external oscillators feeding a PLL and prescalers for the system, AHB and APB clocks, with flash wait states set for speed and peripheral clocks enabled before register access
C.timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement
D.independent counter that resets the MCU if not refreshed within its timeout; a windowed variant also rejects refreshes that arrive too early, catching runaway loops
8. Which term means: "timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement"?
A.Timer PWM — independent counter that resets the MCU if not refreshed within its timeout; a windowed variant also rejects refreshes that arrive too early, catching runaway loops
B.Timer PWM — timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement
C.Timer PWM — sleep stops only the core, stop halts most clocks with RAM retained and microsecond wake-up, standby powers down to a few microamps with only RTC and wake-up pins alive
D.Timer PWM — each pin set as input, output, alternate function or analog, with push-pull or open-drain driver, pull-up or pull-down selection and output speed setting
A.sleep stops only the core, stop halts most clocks with RAM retained and microsecond wake-up, standby powers down to a few microamps with only RTC and wake-up pins alive
B.Wi-Fi and Bluetooth SoCs with dual Xtensa LX6/LX7 or single RISC-V cores, running ESP-IDF on FreeRTOS with one core commonly reserved for the wireless stack
C.sampling window must be long enough for the sample capacitor to charge through the source impedance, roughly ten time constants, or readings droop with high-impedance sensors
D.internal and external oscillators feeding a PLL and prescalers for the system, AHB and APB clocks, with flash wait states set for speed and peripheral clocks enabled before register access
11. Which term means: "sampling window must be long enough for the sample capacitor to charge through the source impedance, roughly ten time constants, or readings droop with high-impedance sensors"?
A.ADC acquisition time — each pin set as input, output, alternate function or analog, with push-pull or open-drain driver, pull-up or pull-down selection and output speed setting
B.ADC acquisition time — timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement
C.ADC acquisition time — sampling window must be long enough for the sample capacitor to charge through the source impedance, roughly ten time constants, or readings droop with high-impedance sensors
D.ADC acquisition time — internal and external oscillators feeding a PLL and prescalers for the system, AHB and APB clocks, with flash wait states set for speed and peripheral clocks enabled before register access
A.peripheral-to-memory or memory-to-memory transfers without the CPU, configured with source, destination, count, increment mode and circular buffering, completing with an interrupt
B.timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement
C.sampling window must be long enough for the sample capacitor to charge through the source impedance, roughly ten time constants, or readings droop with high-impedance sensors
D.nested vectored interrupt controller with programmable priorities, pre-emption, tail-chaining and automatic register stacking so handlers are ordinary C functions
14. Which term means: "peripheral-to-memory or memory-to-memory transfers without the CPU, configured with source, destination, count, increment mode and circular buffering, completing with an interrupt"?
A.DMA — nested vectored interrupt controller with programmable priorities, pre-emption, tail-chaining and automatic register stacking so handlers are ordinary C functions
B.DMA — peripheral-to-memory or memory-to-memory transfers without the CPU, configured with source, destination, count, increment mode and circular buffering, completing with an interrupt
C.DMA — each pin set as input, output, alternate function or analog, with push-pull or open-drain driver, pull-up or pull-down selection and output speed setting
D.DMA — sampling window must be long enough for the sample capacitor to charge through the source impedance, roughly ten time constants, or readings droop with high-impedance sensors
A.nested vectored interrupt controller with programmable priorities, pre-emption, tail-chaining and automatic register stacking so handlers are ordinary C functions
B.independent counter that resets the MCU if not refreshed within its timeout; a windowed variant also rejects refreshes that arrive too early, catching runaway loops
C.each pin set as input, output, alternate function or analog, with push-pull or open-drain driver, pull-up or pull-down selection and output speed setting
D.timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement
17. Which term means: "independent counter that resets the MCU if not refreshed within its timeout; a windowed variant also rejects refreshes that arrive too early, catching runaway loops"?
A.Watchdog timer — sampling window must be long enough for the sample capacitor to charge through the source impedance, roughly ten time constants, or readings droop with high-impedance sensors
B.Watchdog timer — independent counter that resets the MCU if not refreshed within its timeout; a windowed variant also rejects refreshes that arrive too early, catching runaway loops
C.Watchdog timer — each pin set as input, output, alternate function or analog, with push-pull or open-drain driver, pull-up or pull-down selection and output speed setting
D.Watchdog timer — internal and external oscillators feeding a PLL and prescalers for the system, AHB and APB clocks, with flash wait states set for speed and peripheral clocks enabled before register access
A.timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement
B.Wi-Fi and Bluetooth SoCs with dual Xtensa LX6/LX7 or single RISC-V cores, running ESP-IDF on FreeRTOS with one core commonly reserved for the wireless stack
C.internal and external oscillators feeding a PLL and prescalers for the system, AHB and APB clocks, with flash wait states set for speed and peripheral clocks enabled before register access
D.sampling window must be long enough for the sample capacitor to charge through the source impedance, roughly ten time constants, or readings droop with high-impedance sensors
20. Which term means: "internal and external oscillators feeding a PLL and prescalers for the system, AHB and APB clocks, with flash wait states set for speed and peripheral clocks enabled before register access"?
A.Clock tree — internal and external oscillators feeding a PLL and prescalers for the system, AHB and APB clocks, with flash wait states set for speed and peripheral clocks enabled before register access
B.Clock tree — each pin set as input, output, alternate function or analog, with push-pull or open-drain driver, pull-up or pull-down selection and output speed setting
C.Clock tree — timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement
D.Clock tree — peripheral-to-memory or memory-to-memory transfers without the CPU, configured with source, destination, count, increment mode and circular buffering, completing with an interrupt
A.peripheral-to-memory or memory-to-memory transfers without the CPU, configured with source, destination, count, increment mode and circular buffering, completing with an interrupt
B.each pin set as input, output, alternate function or analog, with push-pull or open-drain driver, pull-up or pull-down selection and output speed setting
C.sleep stops only the core, stop halts most clocks with RAM retained and microsecond wake-up, standby powers down to a few microamps with only RTC and wake-up pins alive
D.timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement
23. Which term means: "sleep stops only the core, stop halts most clocks with RAM retained and microsecond wake-up, standby powers down to a few microamps with only RTC and wake-up pins alive"?
A.Low-power modes — internal and external oscillators feeding a PLL and prescalers for the system, AHB and APB clocks, with flash wait states set for speed and peripheral clocks enabled before register access
B.Low-power modes — sleep stops only the core, stop halts most clocks with RAM retained and microsecond wake-up, standby powers down to a few microamps with only RTC and wake-up pins alive
C.Low-power modes — independent counter that resets the MCU if not refreshed within its timeout; a windowed variant also rejects refreshes that arrive too early, catching runaway loops
D.Low-power modes — Wi-Fi and Bluetooth SoCs with dual Xtensa LX6/LX7 or single RISC-V cores, running ESP-IDF on FreeRTOS with one core commonly reserved for the wireless stack
A.Wi-Fi and Bluetooth SoCs with dual Xtensa LX6/LX7 or single RISC-V cores, running ESP-IDF on FreeRTOS with one core commonly reserved for the wireless stack
B.peripheral-to-memory or memory-to-memory transfers without the CPU, configured with source, destination, count, increment mode and circular buffering, completing with an interrupt
C.independent counter that resets the MCU if not refreshed within its timeout; a windowed variant also rejects refreshes that arrive too early, catching runaway loops
D.nested vectored interrupt controller with programmable priorities, pre-emption, tail-chaining and automatic register stacking so handlers are ordinary C functions
26. Which term means: "Wi-Fi and Bluetooth SoCs with dual Xtensa LX6/LX7 or single RISC-V cores, running ESP-IDF on FreeRTOS with one core commonly reserved for the wireless stack"?
A.ESP32 family — sampling window must be long enough for the sample capacitor to charge through the source impedance, roughly ten time constants, or readings droop with high-impedance sensors
B.ESP32 family — peripheral-to-memory or memory-to-memory transfers without the CPU, configured with source, destination, count, increment mode and circular buffering, completing with an interrupt
C.ESP32 family — timer counts to an auto-reload value that fixes frequency while a compare register fixes duty cycle, producing pulse-width modulation with no CPU involvement
D.ESP32 family — Wi-Fi and Bluetooth SoCs with dual Xtensa LX6/LX7 or single RISC-V cores, running ESP-IDF on FreeRTOS with one core commonly reserved for the wireless stack
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