27 real Static Timing Analysis questions from the VLSI Design bank, as asked in Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd — free to start.
1. What is Setup time?
Junior
A.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
B.minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
C.path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
D.required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
2. Which term means: "minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock"?
A.Setup time — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
B.Setup time — minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
C.Setup time — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
D.Setup time — OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
A.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
B.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
C.Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
D.minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
5. Which term means: "minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers"?
A.Hold time — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
B.Hold time — Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
C.Hold time — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
D.Hold time — required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
A.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
B.minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
C.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
D.required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
8. Which term means: "required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report"?
A.Slack — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
B.Slack — required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
C.Slack — timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
D.Slack — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
A.path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
B.required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
C.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
D.difference in clock arrival between launch and capture flops; positive values help setup and hurt hold, so useful skew can be introduced deliberately
11. Which term means: "difference in clock arrival between launch and capture flops; positive values help setup and hurt hold, so useful skew can be introduced deliberately"?
A.Clock skew — difference in clock arrival between launch and capture flops; positive values help setup and hurt hold, so useful skew can be introduced deliberately
B.Clock skew — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
C.Clock skew — minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
D.Clock skew — OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
A.path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
B.minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
C.Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
D.minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
14. Which term means: "path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check"?
A.Multicycle path — minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
B.Multicycle path — required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
C.Multicycle path — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
D.Multicycle path — path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
A.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
B.OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
C.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
D.minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
17. Which term means: "timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation"?
A.False path — required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
B.False path — OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
C.False path — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
D.False path — timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
A.minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
B.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
C.OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
D.path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
20. Which term means: "checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases"?
A.Recovery and removal — path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
B.Recovery and removal — checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
C.Recovery and removal — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
D.Recovery and removal — required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
A.OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
B.path constrained with set_multicycle_path to allow N cycles between launch and capture, requiring a matching hold adjustment of N − 1 to avoid an impossibly tight hold check
C.minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
D.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
23. Which term means: "OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes"?
A.On-chip variation derating — difference in clock arrival between launch and capture flops; positive values help setup and hurt hold, so useful skew can be introduced deliberately
B.On-chip variation derating — Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
C.On-chip variation derating — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
D.On-chip variation derating — OCV applies flat early/late derates, AOCV scales them with logic depth and distance, POCV uses per-cell statistical sigma, reducing pessimism at advanced nodes
A.checks on asynchronous reset de-assertion relative to the clock edge, analogous to setup and hold, ensuring the flop does not go metastable when reset releases
B.required time minus arrival time at an endpoint; a negative value is a violation, and the worst negative endpoint is the headline number of a timing report
C.Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
D.timing path that can never be exercised functionally, such as between mutually exclusive modes or test-only logic, excluded with set_false_path so it does not distort optimisation
26. Which term means: "Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation"?
A.PrimeTime signoff — minimum interval data must remain stable after the capturing edge; violations come from too-short paths, are independent of clock frequency and are fixed with delay buffers
B.PrimeTime signoff — Synopsys timing engine used for final multi-corner multi-mode signoff with signal-integrity analysis, common-path pessimism removal and ECO generation
C.PrimeTime signoff — difference in clock arrival between launch and capture flops; positive values help setup and hurt hold, so useful skew can be introduced deliberately
D.PrimeTime signoff — minimum interval data must be stable before the capturing clock edge; violated when launch delay plus logic delay exceeds the period minus this margin, fixed by faster logic or a slower clock
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