27 real Debugging & Tools questions from the Embedded Systems bank, as asked in Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd — free to start.
1. What is JTAG versus SWD?
Junior
A.use a 10× probe with a short ground lead and bandwidth at least five times the signal frequency, and check compensation, since a long ground lead rings at tens of MHz
B.four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
C.read CFSR, HFSR, BFAR and MMFAR plus the stacked PC and LR in the fault handler to find the faulting instruction, typically a null pointer, misaligned access or stack overflow
D.captures many digital channels simultaneously with protocol decoders for SPI, I2C and UART, triggering on patterns to correlate bus traffic with firmware events
2. Which term means: "four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port"?
A.JTAG versus SWD — dedicated hardware such as a CAN or USB analyser capturing and decoding traffic at line rate with timestamps and error frames the MCU itself cannot observe
B.JTAG versus SWD — four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
C.JTAG versus SWD — OpenOCD drives the probe and exposes a GDB server on port 3333, so gdb can load, halt, single-step and set hardware breakpoints and watchpoints on the target
D.JTAG versus SWD — use a 10× probe with a short ground lead and bandwidth at least five times the signal frequency, and check compensation, since a long ground lead rings at tens of MHz
A.captures many digital channels simultaneously with protocol decoders for SPI, I2C and UART, triggering on patterns to correlate bus traffic with firmware events
B.OpenOCD drives the probe and exposes a GDB server on port 3333, so gdb can load, halt, single-step and set hardware breakpoints and watchpoints on the target
C.four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
D.dedicated hardware such as a CAN or USB analyser capturing and decoding traffic at line rate with timestamps and error frames the MCU itself cannot observe
5. Which term means: "OpenOCD drives the probe and exposes a GDB server on port 3333, so gdb can load, halt, single-step and set hardware breakpoints and watchpoints on the target"?
A.GDB and OpenOCD — debug printf through the ITM/SWO pin or through semihosting breakpoints without a UART; SWO is low-intrusion, semihosting halts the core and distorts timing
B.GDB and OpenOCD — captures many digital channels simultaneously with protocol decoders for SPI, I2C and UART, triggering on patterns to correlate bus traffic with firmware events
C.GDB and OpenOCD — embedded trace macrocell streaming executed instruction flow to a trace probe, giving non-intrusive reconstruction of crashes and code coverage on real hardware
D.GDB and OpenOCD — OpenOCD drives the probe and exposes a GDB server on port 3333, so gdb can load, halt, single-step and set hardware breakpoints and watchpoints on the target
A.OpenOCD drives the probe and exposes a GDB server on port 3333, so gdb can load, halt, single-step and set hardware breakpoints and watchpoints on the target
B.use a 10× probe with a short ground lead and bandwidth at least five times the signal frequency, and check compensation, since a long ground lead rings at tens of MHz
C.embedded trace macrocell streaming executed instruction flow to a trace probe, giving non-intrusive reconstruction of crashes and code coverage on real hardware
D.four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
8. Which term means: "use a 10× probe with a short ground lead and bandwidth at least five times the signal frequency, and check compensation, since a long ground lead rings at tens of MHz"?
A.Oscilloscope probing basics — read CFSR, HFSR, BFAR and MMFAR plus the stacked PC and LR in the fault handler to find the faulting instruction, typically a null pointer, misaligned access or stack overflow
B.Oscilloscope probing basics — compiling logic off-target with Unity/CMock or GoogleTest and mocking the hardware access layer, so business logic is tested on the host in CI
C.Oscilloscope probing basics — embedded trace macrocell streaming executed instruction flow to a trace probe, giving non-intrusive reconstruction of crashes and code coverage on real hardware
D.Oscilloscope probing basics — use a 10× probe with a short ground lead and bandwidth at least five times the signal frequency, and check compensation, since a long ground lead rings at tens of MHz
A.embedded trace macrocell streaming executed instruction flow to a trace probe, giving non-intrusive reconstruction of crashes and code coverage on real hardware
B.read CFSR, HFSR, BFAR and MMFAR plus the stacked PC and LR in the fault handler to find the faulting instruction, typically a null pointer, misaligned access or stack overflow
C.OpenOCD drives the probe and exposes a GDB server on port 3333, so gdb can load, halt, single-step and set hardware breakpoints and watchpoints on the target
D.captures many digital channels simultaneously with protocol decoders for SPI, I2C and UART, triggering on patterns to correlate bus traffic with firmware events
11. Which term means: "captures many digital channels simultaneously with protocol decoders for SPI, I2C and UART, triggering on patterns to correlate bus traffic with firmware events"?
A.Logic analyser — four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
B.Logic analyser — compiling logic off-target with Unity/CMock or GoogleTest and mocking the hardware access layer, so business logic is tested on the host in CI
C.Logic analyser — dedicated hardware such as a CAN or USB analyser capturing and decoding traffic at line rate with timestamps and error frames the MCU itself cannot observe
D.Logic analyser — captures many digital channels simultaneously with protocol decoders for SPI, I2C and UART, triggering on patterns to correlate bus traffic with firmware events
A.four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
B.dedicated hardware such as a CAN or USB analyser capturing and decoding traffic at line rate with timestamps and error frames the MCU itself cannot observe
C.captures many digital channels simultaneously with protocol decoders for SPI, I2C and UART, triggering on patterns to correlate bus traffic with firmware events
D.embedded trace macrocell streaming executed instruction flow to a trace probe, giving non-intrusive reconstruction of crashes and code coverage on real hardware
14. Which term means: "dedicated hardware such as a CAN or USB analyser capturing and decoding traffic at line rate with timestamps and error frames the MCU itself cannot observe"?
A.Protocol analyser — compiling logic off-target with Unity/CMock or GoogleTest and mocking the hardware access layer, so business logic is tested on the host in CI
B.Protocol analyser — read CFSR, HFSR, BFAR and MMFAR plus the stacked PC and LR in the fault handler to find the faulting instruction, typically a null pointer, misaligned access or stack overflow
C.Protocol analyser — captures many digital channels simultaneously with protocol decoders for SPI, I2C and UART, triggering on patterns to correlate bus traffic with firmware events
D.Protocol analyser — dedicated hardware such as a CAN or USB analyser capturing and decoding traffic at line rate with timestamps and error frames the MCU itself cannot observe
A.debug printf through the ITM/SWO pin or through semihosting breakpoints without a UART; SWO is low-intrusion, semihosting halts the core and distorts timing
B.embedded trace macrocell streaming executed instruction flow to a trace probe, giving non-intrusive reconstruction of crashes and code coverage on real hardware
C.four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
D.use a 10× probe with a short ground lead and bandwidth at least five times the signal frequency, and check compensation, since a long ground lead rings at tens of MHz
17. Which term means: "debug printf through the ITM/SWO pin or through semihosting breakpoints without a UART; SWO is low-intrusion, semihosting halts the core and distorts timing"?
A.Semihosting and SWO tracing — dedicated hardware such as a CAN or USB analyser capturing and decoding traffic at line rate with timestamps and error frames the MCU itself cannot observe
B.Semihosting and SWO tracing — read CFSR, HFSR, BFAR and MMFAR plus the stacked PC and LR in the fault handler to find the faulting instruction, typically a null pointer, misaligned access or stack overflow
C.Semihosting and SWO tracing — debug printf through the ITM/SWO pin or through semihosting breakpoints without a UART; SWO is low-intrusion, semihosting halts the core and distorts timing
D.Semihosting and SWO tracing — compiling logic off-target with Unity/CMock or GoogleTest and mocking the hardware access layer, so business logic is tested on the host in CI
A.four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
B.compiling logic off-target with Unity/CMock or GoogleTest and mocking the hardware access layer, so business logic is tested on the host in CI
C.use a 10× probe with a short ground lead and bandwidth at least five times the signal frequency, and check compensation, since a long ground lead rings at tens of MHz
D.debug printf through the ITM/SWO pin or through semihosting breakpoints without a UART; SWO is low-intrusion, semihosting halts the core and distorts timing
20. Which term means: "compiling logic off-target with Unity/CMock or GoogleTest and mocking the hardware access layer, so business logic is tested on the host in CI"?
A.Unit testing embedded code — compiling logic off-target with Unity/CMock or GoogleTest and mocking the hardware access layer, so business logic is tested on the host in CI
B.Unit testing embedded code — OpenOCD drives the probe and exposes a GDB server on port 3333, so gdb can load, halt, single-step and set hardware breakpoints and watchpoints on the target
C.Unit testing embedded code — four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
D.Unit testing embedded code — captures many digital channels simultaneously with protocol decoders for SPI, I2C and UART, triggering on patterns to correlate bus traffic with firmware events
A.captures many digital channels simultaneously with protocol decoders for SPI, I2C and UART, triggering on patterns to correlate bus traffic with firmware events
B.use a 10× probe with a short ground lead and bandwidth at least five times the signal frequency, and check compensation, since a long ground lead rings at tens of MHz
C.four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
D.read CFSR, HFSR, BFAR and MMFAR plus the stacked PC and LR in the fault handler to find the faulting instruction, typically a null pointer, misaligned access or stack overflow
23. Which term means: "read CFSR, HFSR, BFAR and MMFAR plus the stacked PC and LR in the fault handler to find the faulting instruction, typically a null pointer, misaligned access or stack overflow"?
A.Hard fault analysis — read CFSR, HFSR, BFAR and MMFAR plus the stacked PC and LR in the fault handler to find the faulting instruction, typically a null pointer, misaligned access or stack overflow
B.Hard fault analysis — use a 10× probe with a short ground lead and bandwidth at least five times the signal frequency, and check compensation, since a long ground lead rings at tens of MHz
C.Hard fault analysis — debug printf through the ITM/SWO pin or through semihosting breakpoints without a UART; SWO is low-intrusion, semihosting halts the core and distorts timing
D.Hard fault analysis — captures many digital channels simultaneously with protocol decoders for SPI, I2C and UART, triggering on patterns to correlate bus traffic with firmware events
A.four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
B.OpenOCD drives the probe and exposes a GDB server on port 3333, so gdb can load, halt, single-step and set hardware breakpoints and watchpoints on the target
C.dedicated hardware such as a CAN or USB analyser capturing and decoding traffic at line rate with timestamps and error frames the MCU itself cannot observe
D.embedded trace macrocell streaming executed instruction flow to a trace probe, giving non-intrusive reconstruction of crashes and code coverage on real hardware
26. Which term means: "embedded trace macrocell streaming executed instruction flow to a trace probe, giving non-intrusive reconstruction of crashes and code coverage on real hardware"?
A.Instruction trace (ETM) — dedicated hardware such as a CAN or USB analyser capturing and decoding traffic at line rate with timestamps and error frames the MCU itself cannot observe
B.Instruction trace (ETM) — embedded trace macrocell streaming executed instruction flow to a trace probe, giving non-intrusive reconstruction of crashes and code coverage on real hardware
C.Instruction trace (ETM) — compiling logic off-target with Unity/CMock or GoogleTest and mocking the hardware access layer, so business logic is tested on the host in CI
D.Instruction trace (ETM) — four or five-wire JTAG versus ARM's two-wire Serial Wire Debug (SWDIO, SWCLK) giving the same core access with fewer pins, both reaching the debug access port
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