27 real Communication Protocols questions from the Embedded Systems bank, as asked in Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd — free to start.
1. What is UART framing?
Junior
A.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
B.asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
C.differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
D.two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
2. Which term means: "asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%"?
A.UART framing — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
B.UART framing — asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
C.UART framing — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
D.UART framing — host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver
A.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
B.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
C.CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
D.synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
5. Which term means: "synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA"?
A.SPI — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
B.SPI — CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
C.SPI — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
D.SPI — two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
A.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
B.synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
C.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
D.two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
8. Which term means: "two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed"?
A.I2C — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
B.I2C — two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
C.I2C — master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
D.I2C — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
A.differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
B.two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
C.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
D.bitwise non-destructive contest on the identifier where a dominant 0 beats a recessive 1, so the lowest ID wins without losing time, at up to 1 Mbit/s classic or 8 Mbit/s CAN FD data phase
11. Which term means: "bitwise non-destructive contest on the identifier where a dominant 0 beats a recessive 1, so the lowest ID wins without losing time, at up to 1 Mbit/s classic or 8 Mbit/s CAN FD data phase"?
A.CAN arbitration — bitwise non-destructive contest on the identifier where a dominant 0 beats a recessive 1, so the lowest ID wins without losing time, at up to 1 Mbit/s classic or 8 Mbit/s CAN FD data phase
B.CAN arbitration — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
C.CAN arbitration — asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
D.CAN arbitration — host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver
A.differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
B.synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
C.CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
D.asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
14. Which term means: "differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing"?
A.RS-485 — asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
B.RS-485 — two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
C.RS-485 — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
D.RS-485 — differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
A.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
B.host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver
C.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
D.synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
17. Which term means: "master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames"?
A.Modbus RTU — two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
B.Modbus RTU — host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver
C.Modbus RTU — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
D.Modbus RTU — master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
A.asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
B.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
C.host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver
D.differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
20. Which term means: "single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame"?
A.LIN — differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
B.LIN — single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
C.LIN — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
D.LIN — two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
A.host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver
B.differential half-duplex multi-drop physical layer over twisted pair supporting 32 or more nodes up to 1200 m, needing 120 Ω termination and fail-safe biasing
C.asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
D.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
23. Which term means: "host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver"?
A.USB enumeration — bitwise non-destructive contest on the identifier where a dominant 0 beats a recessive 1, so the lowest ID wins without losing time, at up to 1 Mbit/s classic or 8 Mbit/s CAN FD data phase
B.USB enumeration — CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
C.USB enumeration — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
D.USB enumeration — host detects a device by the pull-up on D+ or D−, resets it, reads descriptors at address 0 over endpoint 0, assigns an address and loads the class driver
A.single-wire 20 kbit/s master-slave bus for low-cost automotive body electronics, with a master-driven schedule table and a break-sync-identifier header per frame
B.two-wire open-drain bus with SDA and SCL needing pull-ups, 7-bit addressing, ACK per byte and speeds of 100 kHz standard, 400 kHz fast and 3.4 MHz high-speed
C.CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
D.master-slave protocol over RS-485 with function codes for reading and writing coils and registers, CRC-16 per frame and 3.5-character silent intervals delimiting frames
26. Which term means: "CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256"?
A.CAN error handling — synchronous full-duplex master-slave bus with SCLK, MOSI, MISO and one chip-select per slave, running tens of MHz with clock polarity and phase set by CPOL and CPHA
B.CAN error handling — CRC, bit-stuffing, form and ACK checks raise error frames, and transmit/receive error counters move a node to error-passive at 128 and bus-off at 256
C.CAN error handling — bitwise non-destructive contest on the identifier where a dominant 0 beats a recessive 1, so the lowest ID wins without losing time, at up to 1 Mbit/s classic or 8 Mbit/s CAN FD data phase
D.CAN error handling — asynchronous serial with a start bit, 5–9 data bits sent LSB first, optional parity and 1–2 stop bits, both ends agreeing on baud rate within about 2–3%
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