27 real Computer Architecture & SoC questions from the VLSI Design bank, as asked in Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd — free to start.
1. What is Pipeline hazards?
Junior
A.keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
B.data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
C.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
D.ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
2. Which term means: "data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling"?
A.Pipeline hazards — ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
B.Pipeline hazards — packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
C.Pipeline hazards — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
D.Pipeline hazards — data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
A.direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
B.data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
C.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
D.keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
5. Which term means: "direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time"?
A.Cache mapping — data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
B.Cache mapping — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
C.Cache mapping — ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
D.Cache mapping — GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
A.ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
B.direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
C.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
D.GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
8. Which term means: "ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic"?
A.AMBA bus family — ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
B.AMBA bus family — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
C.AMBA bus family — keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
D.AMBA bus family — rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics
A.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
B.five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
C.data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
D.packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
11. Which term means: "five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions"?
A.AXI channels — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
B.AXI channels — five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
C.AXI channels — keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
D.AXI channels — open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
A.five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
B.packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
C.rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics
D.GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
14. Which term means: "packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels"?
A.Network-on-chip — ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
B.Network-on-chip — data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
C.Network-on-chip — packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
D.Network-on-chip — rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics
A.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
B.five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
C.GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
D.keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
17. Which term means: "open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions"?
A.RISC-V — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
B.RISC-V — packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
C.RISC-V — keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
D.RISC-V — open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
A.ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
B.GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
C.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
D.five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
20. Which term means: "GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling"?
A.Interrupt controller — five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
B.Interrupt controller — data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
C.Interrupt controller — ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
D.Interrupt controller — GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
A.keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
B.five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
C.GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
D.ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
23. Which term means: "keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs"?
A.Cache coherence — keeping copies of a line consistent across cores using snooping MESI-style states or a directory, carried by ACE or CHI protocols in ARM SoCs
B.Cache coherence — GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
C.Cache coherence — five independent channels for read address, read data, write address, write data and write response, each with VALID/READY handshake allowing outstanding and out-of-order transactions
D.Cache coherence — open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
A.rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics
B.ARM's open on-chip interconnect standards: APB for low-speed peripherals, AHB for medium bandwidth and AXI for high-performance burst traffic
C.open royalty-free ISA with a small base integer set and optional extensions M, A, F, D, C and V, letting vendors add custom instructions
D.data, control and structural conflicts where an instruction depends on an unfinished predecessor, a branch target or a busy unit, resolved by forwarding, prediction or stalling
26. Which term means: "rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics"?
A.Memory consistency model — packet-switched interconnect of routers and links replacing crossbars in large SoCs, offering scalable bandwidth with quality-of-service and virtual channels
B.Memory consistency model — rules for the order in which loads and stores become visible across cores; ARM and RISC-V are weakly ordered so software needs barriers or acquire/release semantics
C.Memory consistency model — GIC in ARM systems or PLIC in RISC-V prioritising and routing interrupts to cores, supporting shared and private peripheral interrupts and inter-processor signalling
D.Memory consistency model — direct-mapped, set-associative and fully associative placement of memory blocks, trading hit rate against lookup complexity and access time
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