Synopsys India hires freshers mainly as R&D Engineers through campus drives: an MCQ test on aptitude, C/C++ output, OS and digital electronics, then two to four technical interviews and HR. Interviews mix C/C++, OOP, data structures and OS with digital basics such as flip-flops and NAND logic. Applications Engineering is a separate early-career track.
Who can apply
- B.Tech/M.Tech; one reported R&D drive (Noida centre) required CGPA 8.5
- A fresher R&D Engineer posting (Noida, memory compilers) asked for a Bachelor's or Master's in Electrical, Electronics or VLSI, 0-1 years
- Synopsys global early-careers page: internships are for enrolled students, typically penultimate or final year, no prior experience needed
Key facts
- Entry-level software engineer pay (Levels.fyi, level 64, India)
- about ₹15.9 LPA median (reported) [source]
- Entry-level hardware engineer pay (Levels.fyi, Engineer, India)
- about ₹20.3 LPA median (reported) [source]
- Selection at one reported drive
- 14 of about 100 cleared the test; 3 offers [source]
- Early-career tracks
- R&D Engineering and Applications Engineering [source]
What Synopsys India asks — practise by section
Biggest topics to practise
Electronics & Comm. engineering: interview questions · core companies that hire · jobs through GATE
Interview process
- 1Online testFormats vary: 36 MCQs in 1 hour with 50% negative marking (aptitude, C output, CMOS, power, K-maps, flip-flops), or 40 MCQs plus one coding question.
- 2Technical interview 1C/C++ and systems depth: stages of compilation, static vs shared libraries, linker and loader, OOP (virtual tables, polymorphism), plus a coding problem.
- 3Technical interview 2Pointers and dynamic allocation, BST, heap and BFS problems, puzzles, and digital basics such as D flip-flop behaviour and XOR from NAND gates.
- 4HR / managerialProjects, relocation, why Synopsys and career plans; some drives added a further technical round or a second HR round.
Questions to expect in Synopsys India interviews
Drawn from reported fresher tests and interviews (sources below), with short answers. Practise more on placd.
Implement an XOR gate using only NAND gates.
Four NAND gates: n = NAND(A,B); p = NAND(A,n); q = NAND(B,n); Y = NAND(p,q) = A XOR B. Check: A = B = 1 gives n = 0, p = q = 1, Y = 0; A = 1, B = 0 gives n = 1, p = 0, q = 1, Y = 1.
What does the clock do in a D flip-flop, and how is it different from a D latch?
An edge-triggered D flip-flop samples D only at the active clock edge and holds Q until the next edge: Q(next) = D. A D latch is level-sensitive: while enable is active, Q follows D (transparent). D must meet setup and hold time around the edge, or the flop can go metastable.
What causes power dissipation in CMOS, and how do you reduce it?
Dynamic switching power P = alpha x C x Vdd^2 x f (alpha = activity factor), plus short-circuit power during transitions and static leakage (subthreshold, gate). Because power scales with Vdd squared, lowering supply voltage helps most; clock gating cuts switching activity, and power gating or high-Vt cells cut leakage.
Explain the stages of compilation of a C program.
1) Preprocessing: expands #include, macros and conditional code. 2) Compilation: translates to assembly. 3) Assembly: produces an object file of machine code (.o). 4) Linking: resolves symbols across object files and libraries into an executable. At run time the loader maps it into memory, and the dynamic linker loads shared libraries.
What is the difference between static and shared libraries?
A static library (.a, .lib) is copied into the executable at link time: bigger binary, no run-time dependency, relink needed to update. A shared library (.so, .dll) is loaded at run time and shared between processes: smaller binaries and in-place updates, but it must be found at run time (on Linux via system paths or LD_LIBRARY_PATH).
Given array A, build B where B[j] is the product of all A[i] with i != j, in O(N). Example: {2,5,4,10} gives {200,80,100,40}.
Avoid division. Pass left to right storing prefix products: B[j] = product of A[0..j-1]. Then pass right to left with a running suffix product s: B[j] *= s, then s *= A[j]. O(N) time, O(1) extra space besides B, and it handles zeros correctly.
About Synopsys India hiring
Does Synopsys hire ECE students or only CS?
Both. R&D software roles lean on C/C++, data structures and OS, so CS students apply, but the written test includes digital electronics, and fresher R&D postings for memory compilers ask for Electrical, Electronics or VLSI degrees. Applications Engineering is another early-career track open to electronics graduates.
What is the Synopsys written test like?
Reported formats vary: 36 MCQs in one hour worth 1-3 marks each with 50% negative marking (aptitude, C output, digital electronics), 40 MCQs across aptitude, digital and microprocessors, OS and C/C++ plus one coding question, or an untimed test of CS, aptitude and electronics MCQs without negative marking.
How much does Synopsys pay freshers in India?
Synopsys does not publish fresher pay. Levels.fyi reports entry-level medians in India of about ₹15.9 LPA for software engineers (level 64) and about ₹20.3 LPA for hardware engineers. Treat these as reported figures; campus offers vary by role and college.
Sources
- Early Careers - Synopsys
- Synopsys Interview Experience, Set 6 (On-Campus for R&D Engineer) - GeeksforGeeks
- Synopsys Interview Experience, Set 5 (On-Campus for R&D Engineer) - GeeksforGeeks
- Synopsys Interview Experience for R&D Engineer FTE (On-Campus) - GeeksforGeeks
- Synopsys Jobs for Freshers 2025: R&D Engineering, Engineer - FresherOpenings
- Synopsys Software Engineer Salaries in India - Levels.fyi
- Synopsys Hardware Engineer Salaries in India - Levels.fyi
Checked on 25 Sep 2026. Recruitment rules change each cycle — confirm dates and eligibility in the official notification.