Intel India hires most freshers through campus drives, often as graduate interns from M.Tech programmes: a resume and CGPA shortlist, then one to three technical interviews on your project, digital and CMOS basics, C and operating systems, and sometimes an HR round. Its entry-level analog design posting asks for a master's or PhD.
Who can apply
- Master's or PhD in Electrical Engineering or a related STEM field for entry-level analog design roles
- Campus shortlists use CGPA and resume; one reported intern drive used a CGPA 8.5 cutoff
- Hardware roles expect digital electronics, CMOS, Verilog and C
Key facts
- Entry-level pay (India)
- About ₹20 LPA total comp at Grade 5, Intel's lowest India hardware level on Levels.fyi, typically 1–3 years (reported) [source]
- Entry-level analog design posting
- Analog Circuit Design Engineer, Bangalore: entry level, master's or PhD required [source]
- How candidates got interviews
- 49% reported getting the interview via campus recruiting (60 Graduate Technical Intern interviews listed on Glassdoor) [source]
- Interview length
- One reported graduate intern interview was a single 1.5-hour round [source]
What Intel India asks — practise by section
Biggest topics to practise
Electronics & Comm. engineering: interview questions · core companies that hire · jobs through GATE
Interview process
- 1ShortlistResume and CGPA screen through the placement cell; one reported drive shortlisted 6 of about 35 students.
- 2Technical interview 1Project discussion (15-20 minutes), then fundamentals: digital logic and CMOS for hardware roles, C, pointers and bit manipulation.
- 3Technical interview 2Operating systems (scheduling, semaphores, paging, interrupts, MMU) and coding. Some drives use one long round of about 1.5 hours instead.
- 4HR / behaviouralCareer goals and ethics scenarios, such as how you would respond to a bribe.
Questions to expect in Intel India interviews
Drawn from reported fresher tests and interviews (sources below), with short answers. Practise more on placd.
What is the difference between a D latch and a D flip-flop?
A D latch is level-sensitive: while enable is high the output follows D (transparent), and it holds when enable goes low. A D flip-flop is edge-triggered: it samples D only at the clock edge and holds it for the rest of the cycle. A flip-flop is commonly built from two latches in master-slave form with opposite enables.
Explain how a CMOS 2-input NOR gate works.
Two PMOS in series connect VDD to the output and two NMOS in parallel connect the output to ground. If either input is 1, its NMOS conducts and one series PMOS is off, so the output is 0. Only when both inputs are 0 are both PMOS on and both NMOS off, giving 1. Series PMOS make NOR slower than NAND, so they are sized wider.
How do you check whether a number is a power of 2 using bitwise operators?
A power of two has exactly one bit set, so n & (n - 1) clears that bit and gives 0. Test: (n > 0) && ((n & (n - 1)) == 0). Example: 8 = 1000 and 7 = 0111, so 8 & 7 = 0. For 6 = 110, 6 & 5 = 100, which is not zero.
Swap two integers without a temporary variable using XOR.
a ^= b; b ^= a; a ^= b; It works because x ^ x = 0 and x ^ 0 = x. It fails when both operands are the same memory location (for example, swapping an array element with itself through pointers): the first step zeroes it. In practice a temporary variable is clearer and just as fast.
What is the difference between a mutex and a semaphore?
A mutex is a lock with ownership: the thread that locks it must unlock it, and it guards one critical section. A semaphore is a counter with wait (P) and signal (V); a counting semaphore lets up to N users share a resource, and any thread or ISR may signal it, so it is also used for signalling between tasks.
What is the difference between paging and segmentation?
Paging splits memory into fixed-size pages and frames; it avoids external fragmentation but can waste part of the last page (internal fragmentation) and is invisible to the programmer. Segmentation uses variable-size logical units such as code, data and stack, each with a base and limit; it matches program structure but suffers external fragmentation. Many systems combine both.
About Intel India hiring
Does Intel India hire B.Tech freshers for chip design?
Reported Intel India campus interviews are mostly with M.Tech students, and its entry-level Analog Circuit Design Engineer posting requires a master's or PhD. B.Tech ECE students should still watch Intel's careers site and campus drives, but a postgraduate VLSI degree is the more common route into design roles.
What does Intel ask freshers in technical interviews?
Reported questions cover digital basics (latch vs flip-flop, CMOS inverter and NOR gate), C (pointers, power-of-two checks, XOR swap) and operating systems (semaphores, paging, interrupts, MMU). Interviewers usually start with your project, so be ready to defend every design choice on your resume.
How much does Intel India pay entry-level hardware engineers?
Levels.fyi reports about ₹20 lakh a year total compensation at Grade 5, the lowest India hardware engineer level it lists, typically held by engineers with 1–3 years of experience. Intern stipends and campus offers vary by college and year, so treat these as reported figures.
Sources
- Intel careers - Analog Circuit Design Engineer, Bangalore (entry level)
- Levels.fyi - Intel hardware engineer salaries in India
- GeeksforGeeks - Intel interview experience for Graduate Intern (on-campus)
- GeeksforGeeks - Intel interview experience
- GeeksforGeeks - Intel interview experience for internship (on-campus)
- ASIC-System on Chip-VLSI Design - Intel interview questions
- Glassdoor - Intel Graduate Technical Intern interview questions
Checked on 25 Sep 2026. Recruitment rules change each cycle — confirm dates and eligibility in the official notification.