Reported routes into AMD India hardware roles include campus drives and a trainee programme run through VEDA IIT: a written test on logic design, C, aptitude and Verilog or microprocessors, then technical interviews on digital design, FSMs, Verilog, bus protocols and C. Most open India postings on AMD's careers site ask for industry experience.
Who can apply
- Electronics or VLSI background: tests cover logic design, C, aptitude, and Verilog or microprocessors
- No official CGPA cutoff found; campus cutoffs vary by college
- Students can join AMD's University Talent Community on careers.amd.com
Key facts
- Entry-level pay (India)
- About ₹24 LPA total comp at Hardware Engineer II (L5), the lowest India level on Levels.fyi (reported) [source]
- Written test (2022 trainee drive via VEDA IIT)
- 3 hours, 100 marks across logic design, C, aptitude and Verilog or microprocessors (reported) [source]
- India hardware locations
- Design and verification postings are in Hyderabad and Bangalore [source]
What AMD India asks — practise by section
Biggest topics to practise
Electronics & Comm. engineering: interview questions · core companies that hire · jobs through GATE
Interview process
- 1Preliminary test2022 AMD trainee drive run through VEDA IIT (a VLSI training institute): 1 hour, 15 digital electronics and 5 aptitude questions.
- 2Main written testSame VEDA IIT drive: 3 hours, 100 marks: logic design 30, C 30, aptitude and reasoning 30, plus microprocessors or Verilog 10 (reported).
- 3Technical interviewUniversal gates, MUX-based gates, Gray code, latch vs flip-flop, Mealy vs Moore, sequence-detector FSMs, Verilog modelling, UART/SPI/I2C/PCIe and C.
- 4HRBackground questions and willingness to relocate.
Questions to expect in AMD India interviews
Drawn from reported fresher tests and interviews (sources below), with short answers. Practise more on placd.
Realize a NAND gate using 2:1 multiplexers.
A 2:1 MUX gives Y = S'I0 + S I1. First build an inverter: S = B, I0 = 1, I1 = 0 gives B'. Then a second MUX with S = A, I0 = 1, I1 = B' gives 1 when A = 0 and B' when A = 1, so Y = A' + B' = (AB)'. Two MUXes in total.
Realize an OR gate using a 2:1 multiplexer.
Set S = A, I0 = B, I1 = 1. Then Y = A'B + A = A + B. One MUX is enough and no inverter is needed.
What is the difference between Mealy and Moore machines?
In a Moore machine the outputs depend only on the current state, so they change only after a clock edge and are unaffected by input glitches, but it often needs more states. In a Mealy machine the outputs depend on the state and the current inputs, so they respond in the same cycle with fewer states, but input glitches can reach the output.
Design an FSM that detects the sequence 101 with overlap.
Mealy, 3 states: S0 (nothing seen), S1 (seen 1), S2 (seen 10). S0: 1 -> S1, 0 -> S0. S1: 1 -> S1, 0 -> S2. S2: 1 -> S1 with output 1 (the last 1 starts the next match), 0 -> S0. All other transitions output 0. A Moore version needs a fourth state for 101 with output 1.
Convert binary to Gray code.
The MSB stays the same; each lower Gray bit is the XOR of adjacent binary bits: g(i) = b(i+1) XOR b(i), or G = B ^ (B >> 1). Example: binary 1011 gives Gray 1110. To convert back, b(MSB) = g(MSB), then b(i) = b(i+1) XOR g(i).
What are the types of modelling in Verilog?
Gate-level (structural, using primitives such as and, or, nand), dataflow (continuous assign statements, e.g. assign y = a & b;) and behavioural (always and initial blocks with if, case and procedural assignments). Switch-level modelling with nmos and pmos primitives also exists but is rarely used. Real designs mix them: behavioural RTL modules connected structurally.
About AMD India hiring
How does AMD India hire freshers for VLSI roles?
Reported routes are campus drives and a trainee programme run through VEDA IIT, with a written test (logic design, C, aptitude, Verilog or microprocessors) and technical interviews on digital design, FSMs, Verilog, bus protocols and C. Most open India postings on careers.amd.com ask for experience, so students should also join AMD's University Talent Community.
What is asked in the AMD written test?
One reported 2022 trainee drive run through VEDA IIT had a 1-hour preliminary test (15 digital electronics and 5 aptitude questions) and a 3-hour, 100-mark main test: logic design 30, C 30, aptitude 30, and a 10-mark choice of microprocessors or Verilog.
What is the AMD India fresher salary?
Levels.fyi reports about ₹24 lakh a year total compensation at Hardware Engineer II (L5), the lowest India level it lists; many submissions at that level come from engineers with 2–3 years of experience. There is no official fresher figure, so treat any number as reported.
Sources
- GeeksforGeeks - AMD interview experience for hardware profile
- GeeksforGeeks - AMD interview experience for Engineer Trainee
- Levels.fyi - AMD hardware engineer salaries in India
- AMD careers - Students
- AMD careers - job search, India
Checked on 25 Sep 2026. Recruitment rules change each cycle — confirm dates and eligibility in the official notification.