27 real Microprocessors & Microcontrollers questions from the Electrical Core bank, as asked in Indian campus drives and tech interviews. Every question has a verified answer and an AI-tutor explanation on placd — free to start.
1. What is 8085 architecture?
Junior
A.transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
B.peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses
C.8-bit processor with a 16-bit address bus (64 KB), multiplexed AD0–AD7 lines, five hardware interrupts and 74 instructions
D.separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck
A.8085 architecture — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
B.8085 architecture — transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
C.8085 architecture — peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses
D.8085 architecture — 8-bit processor with a 16-bit address bus (64 KB), multiplexed AD0–AD7 lines, five hardware interrupts and 74 instructions
5. Which term means: "single chip integrating CPU, RAM, ROM, timers and I/O ports, unlike a microprocessor that needs external memory and peripherals"?
A.8051 memory organisation — nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
B.8051 memory organisation — transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
C.8051 memory organisation — Harvard-style separation with 4 KB on-chip program ROM, 128 bytes of data RAM, four 8-bit ports and two 16-bit timers
D.8051 memory organisation — separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck
A.8085 interrupt priority — TRAP is non-maskable and highest, followed by RST 7.5, RST 6.5, RST 5.5 and INTR in descending order
B.8085 interrupt priority — nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
C.8085 interrupt priority — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
D.8085 interrupt priority — separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck
14. Which term means: "peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses"?
A.Memory-mapped I/O — nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
B.Memory-mapped I/O — Harvard-style separation with 4 KB on-chip program ROM, 128 bytes of data RAM, four 8-bit ports and two 16-bit timers
C.Memory-mapped I/O — transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
D.Memory-mapped I/O — peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses
17. Which term means: "hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups"?
A.Watchdog timer — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
B.Watchdog timer — nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
C.Watchdog timer — TRAP is non-maskable and highest, followed by RST 7.5, RST 6.5, RST 5.5 and INTR in descending order
D.Watchdog timer — separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck
20. Which term means: "separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck"?
A.Harvard architecture — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
B.Harvard architecture — single chip integrating CPU, RAM, ROM, timers and I/O ports, unlike a microprocessor that needs external memory and peripherals
C.Harvard architecture — separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck
D.Harvard architecture — Harvard-style separation with 4 KB on-chip program ROM, 128 bytes of data RAM, four 8-bit ports and two 16-bit timers
23. Which term means: "nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining"?
A.NVIC — Harvard-style separation with 4 KB on-chip program ROM, 128 bytes of data RAM, four 8-bit ports and two 16-bit timers
B.NVIC — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
C.NVIC — peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses
D.NVIC — nested vectored interrupt controller of ARM Cortex-M providing prioritised nested interrupts with automatic register stacking and tail-chaining
A.DMA controller — separate program and data buses allow simultaneous instruction fetch and data access, avoiding the von Neumann shared-bus bottleneck
B.DMA controller — hardware counter that resets the controller if firmware fails to refresh it within the timeout, recovering from software lockups
C.DMA controller — transfers data between peripherals and memory without CPU involvement, freeing processor cycles for computation
D.DMA controller — peripherals share the memory address space and are accessed with MOV instructions, whereas I/O-mapped devices use IN/OUT with 8-bit port addresses
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