Arch · CPU & Memory interview questions

1. A.the CPU component that performs arithmetic and logical operations on operands
2. B.a design storing instructions and data in the same memory, sharing one bus between CPU and memory
3. C.the repeating sequence of fetch, decode, and execute that the CPU performs for each instruction
4. D.a cache where a memory block may occupy any line, minimizing conflict misses at high lookup cost

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1. A.addressing mode
2. B.memory hierarchy
3. C.direct memory access (DMA)
4. D.von Neumann architecture

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1. A.von Neumann architecture — a cache where each block maps to one set but may sit in any line within it, balancing speed and conflicts
2. B.von Neumann architecture — a design storing instructions and data in the same memory, sharing one bus between CPU and memory
3. C.von Neumann architecture — the layered arrangement of registers, caches, main memory, and disk trading speed against capacity
4. D.von Neumann architecture — the CPU component that performs arithmetic and logical operations on operands

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1. A.the CPU component that performs arithmetic and logical operations on operands
2. B.a small, very fast storage location inside the CPU holding operands and intermediate results
3. C.a design with physically separate memories and buses for instructions and data, allowing parallel access
4. D.a mechanism letting a device transfer data to or from memory without involving the CPU per byte

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1. A.RISC vs CISC
2. B.Harvard architecture
3. C.interrupt
4. D.register

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1. A.Harvard architecture — the tendency of programs to reuse nearby data and recent addresses, which caches exploit
2. B.Harvard architecture — a design with physically separate memories and buses for instructions and data, allowing parallel access
3. C.Harvard architecture — overlapping the execution of multiple instructions across stages to raise instruction throughput
4. D.Harvard architecture — the layered arrangement of registers, caches, main memory, and disk trading speed against capacity

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1. A.a small fast buffer between the CPU and main memory holding recently used data and instructions
2. B.the CPU component that decodes instructions and directs other units by generating control signals
3. C.a cache where a memory block may occupy any line, minimizing conflict misses at high lookup cost
4. D.a small, very fast storage location inside the CPU holding operands and intermediate results

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1. A.interrupt
2. B.von Neumann architecture
3. C.addressing mode
4. D.register

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1. A.register — a small, very fast storage location inside the CPU holding operands and intermediate results
2. B.register — a condition like data, control, or structural conflict that stalls or disrupts a pipeline
3. C.register — a design with physically separate memories and buses for instructions and data, allowing parallel access
4. D.register — overlapping the execution of multiple instructions across stages to raise instruction throughput

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1. A.a small fast buffer between the CPU and main memory holding recently used data and instructions
2. B.a cache where each memory block maps to exactly one cache line, simple but prone to conflicts
3. C.overlapping the execution of multiple instructions across stages to raise instruction throughput
4. D.the CPU component that performs arithmetic and logical operations on operands

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1. A.memory hierarchy
2. B.interrupt
3. C.arithmetic logic unit (ALU)
4. D.set-associative cache

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1. A.arithmetic logic unit (ALU) — the CPU component that performs arithmetic and logical operations on operands
2. B.arithmetic logic unit (ALU) — the layered arrangement of registers, caches, main memory, and disk trading speed against capacity
3. C.arithmetic logic unit (ALU) — a design storing instructions and data in the same memory, sharing one bus between CPU and memory
4. D.arithmetic logic unit (ALU) — the tendency of programs to reuse nearby data and recent addresses, which caches exploit

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1. A.a small fast buffer between the CPU and main memory holding recently used data and instructions
2. B.the CPU component that performs arithmetic and logical operations on operands
3. C.the CPU component that decodes instructions and directs other units by generating control signals
4. D.a mechanism letting a device transfer data to or from memory without involving the CPU per byte

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1. A.cache memory
2. B.instruction cycle
3. C.control unit
4. D.pipelining

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1. A.control unit — a rule specifying how an instruction's operand is located, such as immediate, direct, or indirect
2. B.control unit — a design with physically separate memories and buses for instructions and data, allowing parallel access
3. C.control unit — a small fast buffer between the CPU and main memory holding recently used data and instructions
4. D.control unit — the CPU component that decodes instructions and directs other units by generating control signals

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1. A.the repeating sequence of fetch, decode, and execute that the CPU performs for each instruction
2. B.RISC uses many simple fixed-length instructions, while CISC uses fewer complex variable-length ones
3. C.a rule specifying how an instruction's operand is located, such as immediate, direct, or indirect
4. D.a cache where each block maps to one set but may sit in any line within it, balancing speed and conflicts

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1. A.interrupt
2. B.arithmetic logic unit (ALU)
3. C.locality of reference
4. D.instruction cycle

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1. A.instruction cycle — an asynchronous signal that suspends the CPU's current work to service a higher-priority event
2. B.instruction cycle — the repeating sequence of fetch, decode, and execute that the CPU performs for each instruction
3. C.instruction cycle — the CPU component that performs arithmetic and logical operations on operands
4. D.instruction cycle — a design with physically separate memories and buses for instructions and data, allowing parallel access

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1. A.RISC uses many simple fixed-length instructions, while CISC uses fewer complex variable-length ones
2. B.a design storing instructions and data in the same memory, sharing one bus between CPU and memory
3. C.a cache where a memory block may occupy any line, minimizing conflict misses at high lookup cost
4. D.overlapping the execution of multiple instructions across stages to raise instruction throughput

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1. A.RISC vs CISC
2. B.instruction cycle
3. C.addressing mode
4. D.locality of reference

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1. A.RISC vs CISC — a design with physically separate memories and buses for instructions and data, allowing parallel access
2. B.RISC vs CISC — the repeating sequence of fetch, decode, and execute that the CPU performs for each instruction
3. C.RISC vs CISC — the CPU component that performs arithmetic and logical operations on operands
4. D.RISC vs CISC — RISC uses many simple fixed-length instructions, while CISC uses fewer complex variable-length ones

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1. A.RISC uses many simple fixed-length instructions, while CISC uses fewer complex variable-length ones
2. B.the repeating sequence of fetch, decode, and execute that the CPU performs for each instruction
3. C.a rule specifying how an instruction's operand is located, such as immediate, direct, or indirect
4. D.a small fast buffer between the CPU and main memory holding recently used data and instructions

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1. A.addressing mode
2. B.fully associative cache
3. C.locality of reference
4. D.interrupt

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1. A.addressing mode — a design with physically separate memories and buses for instructions and data, allowing parallel access
2. B.addressing mode — an asynchronous signal that suspends the CPU's current work to service a higher-priority event
3. C.addressing mode — a small, very fast storage location inside the CPU holding operands and intermediate results
4. D.addressing mode — a rule specifying how an instruction's operand is located, such as immediate, direct, or indirect

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1. A.the layered arrangement of registers, caches, main memory, and disk trading speed against capacity
2. B.RISC uses many simple fixed-length instructions, while CISC uses fewer complex variable-length ones
3. C.a cache where each memory block maps to exactly one cache line, simple but prone to conflicts
4. D.a small fast buffer between the CPU and main memory holding recently used data and instructions

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1. A.von Neumann architecture
2. B.register
3. C.memory hierarchy
4. D.pipeline hazard

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1. A.memory hierarchy — a design storing instructions and data in the same memory, sharing one bus between CPU and memory
2. B.memory hierarchy — the layered arrangement of registers, caches, main memory, and disk trading speed against capacity
3. C.memory hierarchy — overlapping the execution of multiple instructions across stages to raise instruction throughput
4. D.memory hierarchy — the CPU component that performs arithmetic and logical operations on operands

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1. A.the CPU component that decodes instructions and directs other units by generating control signals
2. B.a cache where each block maps to one set but may sit in any line within it, balancing speed and conflicts
3. C.a small fast buffer between the CPU and main memory holding recently used data and instructions
4. D.a condition like data, control, or structural conflict that stalls or disrupts a pipeline

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1. A.cache memory
2. B.memory hierarchy
3. C.set-associative cache
4. D.interrupt

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1. A.cache memory — RISC uses many simple fixed-length instructions, while CISC uses fewer complex variable-length ones
2. B.cache memory — an asynchronous signal that suspends the CPU's current work to service a higher-priority event
3. C.cache memory — the tendency of programs to reuse nearby data and recent addresses, which caches exploit
4. D.cache memory — a small fast buffer between the CPU and main memory holding recently used data and instructions

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